IC testing method and IC testing device using the same

ABSTRACT

In an IC testing apparatus which executes a function test and a DC test, a resistor having a high resistance is connected to the output side of a DC tester such that the connection of the resistor allows a function test to operate normally if the DC tester is left connected to the function tester, thus allowing the DC test to be interrupted into the execution of the function test to enable a concurrent execution of the function test and the DC test. As a result, the time required to change switches in the DC tester, for example, can be executed during the function test, thus preventing the time interval required to change the switches from increasing the time interval required for the test, thereby reducing the testing time interval.

TECHNICAL FIELD

The present invention relates to an IC testing method which enables afunction test and a leak current test to be performed in a brief timeinterval when conducting a function test and a direct current (DC) testfor a semiconductor device such as a memory formed by a semiconductorintegrated circuit, and to an IC testing apparatus which employs themethod.

BACKGROUND ART

Heretofore, an IC testing apparatus which tests a semiconductor devicesuch as a memory performs a function test which determines whether ornot the function of the semiconductor device is normally operating and adirect current test which determines whether or not respective terminalsof the semiconductor device exhibit predetermined direct currentcharacteristics. The IC testing apparatus determines an IC which provedto be normal in both the function test and the DC test to be anacceptable product.

FIG. 3 shows a schematic arrangement of an IC testing apparatus. In thisFigure, character TES designates the entire IC testing apparatus. The ICtesting apparatus TES is internally categorized into a main controllerMAIN, a function tester 100 and a DC tester 200.

The main controller MAIN comprises a computer system, and controls thefunction tester 100 and the DC tester 200 through a bus line BUS. Thefunction tester 100 comprises a pattern generator 102, a timinggenerator 104 and function test units 106A, 106B, . . . , 106N.

The function test units 106A-106N are associated with respectiveterminals of an IC tinder test 300 so that switches S₁₁-S_(1n), can beturned on and off to have the function test units 106A-106N connectedwith or disconnected from the respective terminals of the IC under test300.

Thus the function test takes place by controlling the switchesS₁₁-S_(1n) to their on conditions to have the function test units106A-106N connected to the respective terminals of the IC under test 300for applying test pattern signals to the respective terminals of the ICunder test 300 to carry out the function test.

On the other hand, one or more DC testers 200 are provided for testingthe terminals of the IC under test 300 (in the example shown in FIG. 3,the provision of the single DC tester 200 is shown). One or more DCtesters 200 are arranged such that change-over switches S₂₁-S_(2n) arecontrolled to be on such that each DC tester 200 is connected to onlyone of the terminals on the IC under test 300 at a time, thussequentially testing the DC characteristic of the specific terminals.Incidentally, 400 designates a controller which controls these switchesS₁₁-S_(1n) and S₂₁-S_(2n).

FIG. 4 shows an internal arrangement of one of the function test units,106A, and the summary of the function test will be described. Thefunction test unit 106A (the remaining function test units are similarlyarranged) comprises a waveform formatter 11, a driver 12, a voltagecomparator 13, a logical comparator 14 and a fault analysis memory 15.

The waveform formatter 11 receives test pattern data applied from thepattern generator 102 and produces a test pattern signal having anactual waveform. The timing generator 104 supplies a timing signal whichdefines the rise timing and the fall timing of the test pattern signalto the waveform formatter 11.

The test pattern signal delivered from the waveform formatter 11 isshaped by the driver 12 into a waveform of an amplitude having a givenlogical value, which is fed through the switch S₁₁ to a given terminalon the IC under test 300 to store data in the IC under test 300. If thisterminal is an I/O terminal (a combined input and output terminal), theterminal on the IC under test 300 is set into an input mode wheninputting the test pattern signal, and is switched to an output mode atthe time when a write operation is performed. Content stored in the ICunder test 300 is read out when switched into the output mode, and isfed through the voltage comparator 13 to the logical comparator 14.Incidentally, when the voltage comparator 13 reads data delivered fromthe IC under test 300, the output terminal of the driver 12 is set up inits high impedance mode.

The voltage comparator 13 determines by comparison whether the logicsignal read out from the IC under test 300 attains a normal voltagevalue. Thus, voltage comparator 13 determines whether or not L logic andH logic levels are present, for example, 0.8 volt or lower and 2.4 voltor higher, respectively, and for a signal having a voltage that is anormal logic value, the appropriate logic value is input to the logicalcomparator 14.

An expected value is input to the logical comparator 14 from the patterngenerator 102, and is compared against the logic value which is inputfrom the voltage comparator 13, thus detecting the occurrence of anynon-coincidence. In the event a non-coincidence occurs, it is assumedthat there exists a fault in a memory cell it an address where a writeoperation took place, the fault is stored in the fault analysis memory15 at this address, and subsequent to the completion of the test, thenumber of faulty cells is counted by reading out the fault analysismemory 15 to determine whether or not it is possible to salvage the ICunder test 300.

FIG. 5 shows an example of the arrangement of the DC tester 200. Thearrangement shown is one which is used when the DC tester 200 operatesin a voltage applied current measuring mode. A voltage V_(L) or V_(H) isapplied to a non-inverting input terminal of an operational amplifier 16in response to a logic value from a DA converter 17 that is applied to aterminal on the IC under test 300.

A current detecting resistor R1 is connected between the output terminalof the operational amplifier 16 and a current output terminal T_(I), aswitch S_(a2) is connected between the current output terminal T_(I) anda sensing point SEN, a protective resistor R3 is connected between thecurrent output terminal T_(I) and a voltage detecting terminal T_(V),and the voltage detecting terminal T_(V) is connected to the sensingpoint SEN through a switch S_(a1). The sensing point SEN is connectedthrough a change-over switch S₂₁ to a terminal on the IC tinder test300. An inverting input terminal of the operational amplifier 16 isconnected to the voltage detecting terminal T_(V).

Incidentally, a switch S_(b) connected in shunt with the currentdetecting resistor R1 represents a range change-over switch whichchanges the current measuring range. By controlling the switch S_(b) on,a resistor R2 of a smaller resistance, which allows a measurement of ahigh current (a current in the output mode of the IC under test 300), isconnected in circuit, thus changing over to a high current measuringrange.

With this arrangement of the DC tester 200, the voltage V_(L) or V_(H),applied to the non-inverting input terminal of the operational amplifier16 from the DA converter 17 is applied to a terminal on the IC undertest 300 by controlling the switches S_(a1),S_(a2) and the change-overswitch S₂₁ to on conditions.

Specifically, since the operational amplifier 16 operates to makevoltages at the non-inverting and the inverting input terminal equal toeach other, if V_(L), for example, is applied to the non-inverting inputterminal of the operational amplifier 16, the output voltage iscontrolled so that the voltage at the inverting input terminal (equal tothe voltage at the voltage detecting terminal T_(V)) also assumes V_(L).Accordingly, the voltage V_(L) or V_(H), is applied to a terminal on theIC under test 300.

In the DC test mode, each terminal P_(i) of the IC under test 300 is setup in its input mode as shown in FIG. 6. By measuring a current whichpasses through the current detecting resistor R1 under the conditionthat V₁ (a voltage providing an L logic) or V_(H) (a voltage providingan H logic) is applied to the terminal P_(i), respective leak currentsI_(Rek1) and I_(Rek2) of active elements Q1 and Q2 connected to theterminal P_(i) can be measured. Subtractor circuit 18 derives a voltagedeveloped across the current detecting resistor R1, and AD converter 10applies an AD conversion to the voltage obtained by the subtractioncircuit 18 to deliver a digital value.

When measuring the leak currents I_(Rek1), I_(Rek2) passing through eachinput terminal of IC under test 300, change-over switch S_(b) is turnedoff, thus measuring a voltage developed across the current detectingresistor R1 having a relatively high resistance on the order of 100 kΩand measuring the leak currents I_(Rek1) and I_(Rek2) passing througheach input terminal of the IC under test 300. Incidentally, theprotective resistor R3 is formed by a resistor having a relatively smallresistance (on the order of several 10's Ω), thus securing a closedfeedback loop to the inverting input terminal of the operationalamplifier 16 if the switches S_(a1) and S_(a2) are simultaneouslycontrolled to be off during the actual operation. Resistor R3 thusprotects the operational amplifier 16 by preventing an operation thatwould cause the operational amplifier 16 to saturate.

From the foregoing summary, the function test and the DC test in the ICtesting apparatus should be understood. It is to be noted thatheretofore, the function test and the DC test mentioned above have beenperformed in different time intervals, that is to say, after one of thetests is performed, the other test is performed. In particular, in theDC test, it is necessary to provide a control which changes thechange-over switches S₂₁, S₂₂. . . S_(2n) and to provide a control whichchanges the switches S₁₁-S_(1n) shown in FIG. 3. The manner of thesecontrols will be described with reference to FIG. 7.

The function test is performed under the condition that the switchesS_(al), S_(a2) and the change-over switches S₂₁-S_(2n). shown in FIG. 3are all changed to off conditions to disconnect the DC tester 200 fromthe terminals on the IC under test 300 while the switches S₁₁-S_(1n) areall controlled to on conditions. Thus, because the output impedance ofthe DC tester 200 is relatively low on the order of several Ω's, if theDC tester 200 is electrically connected as a load on the function tester100 during the function test, the waveform of a test pattern signalwhich is fed from the function tester 100 to the IC under test 300 isdegraded. This degradation prevents the function test from beingperformed in a normal manner.

For this reason, the function test is performed by controlling all ofthe change-over switches S₂₁-S_(2n), and the switches S_(a1), S_(a2) tooff conditions, which controls the DC tester 200 so that it is notconnected to any terminal on the IC under test 300.

On the other hand, when performing the DC test, switches S₁₁-S_(1n) areall initially controlled to on conditions, which connects the functiontest units 106A-106N to all the terminals on the IC under test 300.Under this condition, an initializing pattern for conducting the DC testis applied to the IC under test 300.

Specifically, if a terminal which is subject to the DC test is an I/Oterminal, an initializing pattern (see FIG. 7C), which sets up an inputmode as the mode for the terminal, is input from the function tester100. After the input mode is set up at the terminal which is subject tothe DC test, that terminal exercises a control which disconnects thefunction test units 106A-106N from all the terminals on the IC undertest 300.

Under this condition, the change-over switch S₂₁ is controlled to be onfor performing the DC test. The DC test measures the leak currentsI_(Rek1) and I_(Rek2) (see FIG. 6) passing through the terminal underthe condition that respective logic values of either H logic or L logicare applied to the terminals on the IC under test 300. If the leakcurrent values are equal to or less than values which are previouslypredetermined, acceptability is determined, while if they are equal toor greater than the values, fault is determined.

In this manner, the DC test is performed for each terminal, and hencethere is required, for each terminal tested, an interval T_(pi) (seeFIG. 7D) equal to the sum of an interval T_(SW1) during which theswitches S₁₁-S_(1n) are controlled on and off in order to apply theinitializing pattern and an interval T_(SW2) during which thechange-over switches S₂₁-S_(2a) are controlled in a switching manner.The interval T_(SW1) for applying the initializing pattern and theinterval T_(SW2) for controlling the change-over switches S₂₁-S_(2n)correspond to a time interval (several ms) for changing the switches(relays), and even if the interval T_(1M) (FIG. 7E) for measuring thecurrent is short, the total interval T_(pi) is relatively long.Accordingly, if a switching control of the switches S₁₁-S_(1n) and thechange-over switches S₂₁-S_(2n) is executed for every terminal, thereresults an inconvenience that the DC test requires a long period oftime. This hinders the testing of large quantities of IC's.

It is an object of the invention to propose an IC testing method capableof testing quantities of IC's in a brief interval by reducing thetesting interval of an IC, and an IC testing apparatus which utilizesthe testing method.

DISCLOSURE OF THE INVENTION

The invention is characterized by an arrangement which allows the DCtester to remain connected to a terminal on an IC under test even duringthe function test, which is enabled by connecting the DC tester to aterminal on the IC under test through a resistor such that theconnection of the resistor prevents the DC tester from presenting asignificant load as viewed from the function tester.

With this arrangement, there is proposed an IC testing method whichpermits the DC test to be executed by controlling the output terminal ofa driver of the function tester to be put into a high impedance modeeven during the function test, thus dispensing with the need for aswitch control to disconnect the function tester during the time the DCtest is being executed and thus allowing an execution of a leak testduring the interval for the functions test.

Thus, with the IC testing method according to the invention, the leaktest for a DC test item is completed at a time coincident with the endof the function test, thus eliminating the need for a special timeinterval to conduct the leak test. Consequently, there is obtained anadvantage that the length of time required for the test can besignificantly reduced.

In addition, the present invention proposes an IC testing apparatuswhich utilizes the IC testing method mentioned above.

An IC testing apparatus according to the invention comprises a functiontester for executing the function test of an IC under test by applying atest pattern signal to each terminal on the IC under test from a driverwhich is capable of setting up a status of an output terminal thereof ina high impedance mode;

a DC tester for measuring a leak current passing through each terminalon an IC under test under a condition that a given voltage is applied toeach terminal on the IC under test;

a resistor connected between the sensing point of the DC tester and theterminal on the IC under test;

first control means for causing a given voltage to be delivered to thesensing point of the DC tester during the execution of the function testby the function tester;

second control means for controlling the output terminal of the driverof the function tester in a high impedance mode at the time a controloperation by the first control means is completed;

and current measuring means for measuring a leak current passing througha terminal of the IC under test under a condition that the outputterminal of the driver is controlled in a high impedance mode.

With the IC testing apparatus according to the invention, there is noneed to disconnect the function tester and the DC tester from each otherduring the execution of the function test and also during the executionof the DC test. Accordingly, the DC test can be executed during theexecution of the function test without a need for the time to change theswitch.

As a consequence, if the DC test is executed during the execution of thefunction test, the DC test is dispersed in a compound form in thefunction test, and there is obtained an advantage that a length of timefor the compounded test cannot be significantly longer than the lengthof time required for the inherent function test, thus allowing thefunction test and a leak test to be completed within a brief interval.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of one embodiment of an IC testing apparatuswhich adopts an IC testing method according to the invention.

FIG. 2 shows timing charts illustrating the IC testing method accordingto the invention.

FIG. 3 is a block diagram schematically illustrating a conventional ICtesting apparatus.

FIG. 4 is a block diagram showing an arrangement of a function testerused in the IC testing apparatus shown in FIG. 3.

FIG. 5 is a circuit diagram illustrating the arrangement of a DC testerused in the IC testing apparatus shown in FIG. 3.

FIG. 6 is a circuit diagram illustrating a situation of a terminal onthe IC under test when executing a leak test for DC test item.

FIG. 7 shows timing charts illustrating the manner of a conventional DCtest.

BEST MODE OF CARRYING OUT THE INVENTION

A more detailed description of the invention will be described withreference to the attached drawings.

FIG. 1 shows an embodiment of an IC testing apparatus which tests an ICunder test 300 according to an IC testing method which is proposed bythe present invention. In this Figure, function tester 100 and DC tester200 are similar to the corresponding components described above inconnection with FIG. 3. When conducting a function test, all of switchesS₁₁-S_(1n) are controlled to be on, thus connecting all the functiontesting units 106A-106N to the respective terminals of IC under test300.

The DC tester 200 sequentially controls one of the change-over switchesS₂₁-S_(2n) to be on, selectively connecting the DC tester 200 to eachterminal of the IC under test 300 to conduct a DC test of each terminalalone, Incidentally, although a plurality of DC testers 200 are providedin actuality to provide an arrangement in which the DC test can becompleted within a brief interval by reducing the number of terminalsundertaken by each tester, the present description assumes that the DCtester 200 is implemented as a single DC tester 200.

The IC testing apparatus according to the invention is characterized inthat in the DC tester 200, a resistor R4 is connected in series with aswitch S2 between the voltage detecting terminal T_(V) and the sensingpoint SEN.

Specifically, in the DC tester 200, a protective resistor R3 connectedbetween a current output terminal T_(I) and a voltage detecting terminalT_(V) is shunted by a first switch S1, while the second switch S2 andthe resistor R4 are connected in series with the voltage detectingterminal T_(V) and sensing point SEN. In addition, a third switch S3 isconnected between the current output terminal T_(I) and the sensingpoint SEN.

When executing the function test, the first switch S1 and the secondswitch S2 are turned on while the third switch S3 is turned off Underthis condition, the resistor R4 is connected in series between thesensing point SEN and the current output terminal T_(I) and the voltagedetecting terminal T_(V). Accordingly, an impedance of the DC tester 200as viewed from the function test unit which is connected to the DCtester 200 can be regarded as the resistance of the resistor R4. Bychoosing a resistance of the resistor R4 to be about 10 kC2, theimpedance of the DC tester 200 as viewed from the function test units106A-106N can be regarded as about 10 kΩ.

A signal transmission line which connects between each of the functiontest units 106A-106N and an IC under test 300 is generally matched to acharacteristic impedance of 50Ω. Accordingly, if a load of 10 kΩ (DCtester 200) were connected to each output of the function test units106A-106N, there can be no significant variation in the line impedance,and the waveform of a test pattern signal which is fed from the functiontesting units 106A-106N to the IC under test 300 cannot be disturbed bythe connection of the DC tester 200. In other words, if the DC tester200 is remains connected to somewhere on the IC under test 300 duringthe function test, the waveform of a test pattern signal applied to theterminal which is connected to the DC tester 200 cannot be disturbed,allowing the function test to be normally executed.

It will be understood from the foregoing description that the functiontest can be executed while DC tester 200 is connected to the functiontest units.

In addition, the present invention proposes a method of executing a DCtest (leak test) during the execution of the function test whilemaintaining the function test units 106A-106N are connected to therespective terminals on the IC under test 300.

Thus, there is proposed a method of measuring a leak current whichpasses through a terminal on the IC under test 300 without controllingthe switches S₁₁-S_(1n) to be off. The method comprises controlling anoutput status of a driver 12 of the function test unit connected to theterminal, the leak current through which is to be measured by the DCtester 200, in a high impedance mode during the time interval a givenvoltage (a voltage providing an H logic or L logic) is applied to suchterminal and measuring a leak current passing through the terminal onthe IC under test 300 by means of DC tester under the condition that thedriver 12 is controlled to be in its high impedance mode.

To this end, during the execution of the function test, a maincontroller MAIN provides a command signal which causes the DC tester 200to produce a given voltage (either L logic or H logic). Specifically, itapplies a digital value for producing a given voltage to a DA converter17. The DA converter 17 effects a DA conversion of the digital value todeliver a voltage V_(L) or V_(H), which is applied to a non-invertinginput terminal of an operational amplifier 16 in DC tester 200.

The operational amplifier 16 operates in a manner such that a voltage atthe voltage detecting terminal T_(V) is equal to the voltage applied tothe non-inverting input terminal. As a consequence, there is produced avoltage at the voltage detecting terminal T_(V) which is equal to theV_(L) or V_(H) supplied by the DA converter 17, and this voltage isapplied to the sensing point SEN through the second switch S2 and theresistor R4, and is then fed to a terminal on IC under test 300 throughone of the change-over switches S₂₁-S_(2n).

During the execution of the function test, the switches S₁₁-S_(1n) andthe switches S1, S2, S4 are all turned on. The time interval to executeDC leak test may be determined, for example, as follows: A DC test timeinterval (a time interval that has a length required to test a singleterminal) as shown in FIG. 2A is previously set up in a function testportion of a test program which is read into the main controller MAIN; acontrol signal HIP is produced during the DC test time interval thatcontrols all the drivers 12 for respective function test units 106A-106Nor driver 12 connected to the terminal which is subject to the DC testto be in a high impedance mode (see FIG. 2D), thus controlling thedriver 12 to be in its high impedance condition while applying a voltagegenerating command to the DC tester so as to control the DC tester 200to generate a given voltage for measuring the leak current.

Incidentally, the DC test time interval, which interrupts the timeinterval of the function test, may be chosen to occur immediately aftera test pattern signal is written into an IC under test 300 to allow theDC test to be executed more quickly since the individual terminals onthe IC under test 300 are already set up in an input mode when the writeoperation takes place.

After the leak test is executed with respect to a single terminal, thefunction test is resumed. During the execution of the function test, thechange-over switches S₂₁-S_(2n) are changed (see FIG. 2E), thusconnecting the DC tester 200 to another terminal. A DC test timeinterval may be provided at any timing position subsequent to thecompletion of such connection for execution of the leak test of a nextterminal.

When change-over switches S₂₁-S_(2n) are changed during the execution ofthe function test in this manner, the time interval required for theleak test which is inserted into the execution of the function test canbe very short, and if the function test and the DC test are executedconcurrently, the overall required time will not be significantly longerthan the length of time required for the function test alone.

Incidentally, a current measuring circuit of the DC tester 200 will bebriefly described. In the present embodiment, a resistor R1 having ahigh resistance (on the order of 100 kΩ) for measuring a minimal current(leak current) and a resistor R2 having a small resistance (on the orderof 100Ω) for measuring a high current (an output current from the ICunder test) are connected in series, thus omitting the range changingswitch S_(b) shown in FIG. 5. Specifically, the minimal currentmeasuring resistor R1 is shunted by diodes D1 and D2. For measurement ofhigh currents, these diodes D1 and D2 are turned on, allowing the highcurrent to be bypassed by diodes D1 or D2, and under this condition, avoltage developed across the resistor R2 is detected by the subtractioncircuit 18B, and fed through switch S5 to the AD converter 19 for ADconversion therein to be input to the main controller MAIN, for example.

On the other hand, when measuring a minimal current, only a voltage onthe order of several tens of mV can be developed across the resistor R1.Accordingly, the diodes D1 and D2 remain off. Thus, by measuring avoltage developed across the resistor R1, a leak current passing througha terminal on an IC under test 300 can be measured. Specifically, avoltage developed across the register R1 is picked out by thesubtraction circuit 18A, and is then fed through the switch S4 to the ADconverter 19 for the AD conversion therein, to be input to the maincontroller MAIN where it is compared against a reference value todetermine if it is acceptable or faulty.

Incidentally, in a high current measuring mode in which a current whichoccurs in an output mode of the IC under test 300 is measured, theswitches S₁₁-S_(1n) are controlled to be off, and the function tester100 is disconnected from the IC under test while only the DC tester 200is connected to the IC under test 300. In addition, within the DC tester200, the first S1 switch is turned off, the second and the third switchS2, S3 are turned on, the switch S4 is turned off, and the switch S5 isturned on for the execution of the DC test.

As described above, with the IC testing method according to theinvention, changing S₂₁-S_(2n) which takes time for its completion dueto their slow response is effected during the execution of the functiontest, and the driver 12 is controlled to its high impedance mode in thecourse of the function test in order to execute the DC test (the leaktest). Accordingly, the function test and the leak test can be completedin a time interval represented by a sum of time intervals required forthe function test and a net time interval required for the DC test(which does not include a time interval to change the switches). As aconsequence, there is obtained an advantage that an overall testing timeinterval may be considerably reduced. It then follows that its effectwill be remarkable when applied in testing quantities of IC's in a brieftime interval by IC manufacturers, for example.

What is claimed is:
 1. A method for use in an IC testing apparatuscomprising a function tester that includes a driver having an outputterminal and a DC tester that includes a sensing point, wherein themethod comprises: controlling the function tester to execute a functiontest of an IC under test by applying a test pattern signal from theoutput terminal to a terminal of the IC under test; connecting thesensing point of the DC tester to the terminal of the IC under testthrough a resistor during execution of the function test of the IC undertest by the function tester, controlling the output terminal of thedriver of the function tester to be in a high impedance condition whilethe DC tester provides a given voltage at the sensing point, controllingthe DC tester to measure a leak current passing through the terminal ofthe IC under test, thereby measuring the leak current during theexecution of the function test.
 2. An IC testing apparatus comprising afunction tester that includes a driver having an output terminal,wherein the function tester executes a function test of an IC under testby applying a test pattern signal from the output terminal to a terminalon the IC under test; a DC tester that includes a sensing point and aresistor connected between the sensing point and the terminal of the ICunder test, wherein the DC tester is adapted to measure a leak currentpassing through the terminal of the IC under test while applying a givenvoltage to the sensing point; first control means for causing the DCtester to apply the given voltage to the sensing point during theexecution of the function test by the function tester; second controlmeans for controlling the output terminal of the driver of the functiontester to be in a high impedance condition at a time when the firstcontrol means causes the DC tester to apply the given voltage to thesensing point; and current measuring means for causing the DC tester tomeasure the leak current passing through the terminal of the IC undertest while the output terminal of the driver is controlled to the highimpedance condition.
 3. An IC testing apparatus according to claim 2wherein the DC tester comprises: an operational amplifier having anon-inverting input terminal, an inverting input terminal and an outputterminal coupled to a current detecting resistor, wherein the givenvoltage is applied to the non-inverting input terminal, an outputvoltage is delivered by the output terminal to the sensing point throughthe current detecting resistor, and the voltage at the sensing pointbeing fed back to the inverting input terminal, and current measuringmeans for measuring a voltage developed across the current detectingresistor to measure the value of a leak current passing through theterminal on the IC under test.
 4. An IC testing apparatus according toclaim 2 wherein the DC tester comprises: an operational amplifier havingan output terminal, a non-inverting input terminal and an invertinginput terminal, a current detecting resistor having one end connected tothe output terminal of the operational amplifier and the other endconnected to a current output terminal, a first switch for applying avoltage delivered at the current output terminal to a voltage detectingterminal, a protective resistor connected between the current outputterminal and the voltage detecting terminal, a feedback circuit forfeeding the voltage at the voltage detecting terminal back to theinverting input terminal of the operational amplifier, a series circuitincluding a second switch and a resistor for applying a voltage at thevoltage detecting terminal to the terminal on the IC under test througha sensing point, a third switch connected between the current outputterminal and the sensing point, and a current measuring means formeasuring a voltage developed across the current detecting resistor tomeasure a current passing through the terminal on the IC under test, andwherein, during execution of the functional test while the leak currentpassing through the terminal on the IC under test is measured, the firstswitch and the second switch are operated so that the DC tester asviewed from the function tester appears to have a high impedance due tothe resistor.
 5. An IC testing apparatus according to claim 4 wherein,when a DC test mode takes place while a function test is not beingexecuted, the first, second and third switches are operated so that thecurrent output terminal is connected directly to the sensing point andto the terminal on the IC under test.